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YGV628B
AVDP7
Advanced Video Display Processor 7 Outline
YGV628B (hereafter called AVDP7) is the latest version of YAMAHA AVDP series which has many past successful records in various visual equipments, vehicle equipment, etc. Three bit-map planes are equipped, and it can be displayed in piles to an external image; furthermore, AVDP7 has many functions as OSD (On Screen Display), such as -blending, change of a display priority, etc. In addition, it has a digital image Input/Output function to allow an external image to be expanded or reduced. Moreover, AVDP7 is supports to the resolution up to SVGA, and it is possible to apply to the various digital equipments only by connecting one SDRAM to an external memory as a frame memory.
Feature
OSD Function
The OSD images which is composed of plains in case of a digital image input is overlaid. Simultaneous use of three plains is possible in AVDP7 at its maximum. The natural picture display of 65536 colors by R5bit, G6bit, and B5bit. It is the palette color of 256 colors in 16777216 colors. Supports 16bit YCrCb422 16 gray-levels of -blending in dot units Conversion of display priority is possible
Display Resolution
Creation of the Display Timing of NTSC, PAL, QVGA, Wide QVGA, VGA, Wide VGA, and SVGA is possible. Examples of Correspondence Resolution : 320x240, 400x240, 720x240, 640x480, 800x480, 800x600, etc.. Resolution Converting Function : Horizontal direction 1/2 times to 8192 times display Vertical direction 1/4 times to 8192 times display.
YGV628B CATALOG CATALOG No.: LSI-4GV628B20 2005.7
YGV628B
Digital Image Input/Output Function
Corresponding to 18bit RGB, 16bit YCrCb422, and ITU656. By YS bit output, Mixing with an image signal are possible externally.
Analog Image Output Function
Analog RGB output which has 8 bits DAC for each R,G,B By YS bit output, super-impose of image data is available from an outside.
Capture Function
The depiction from the external image input of 18bit RGB, 16bit YCrCb422, and ITU656 to frame memory is possible in real time. When the digital image input is ITU656, it is possible to select from two systems of asynchronous input. Pixel Skipping Functions of Horizontal direction and Vertical direction. Interlace Progressive Conversion Function
External Memory
Video Memory 16Mbit, 64Mbit, 128Mbit, and 256Mbit(x16) of SDRAM are connectable. However, only a half domain is possible to use at the time of 256Mbits of SDRAM is in use. WRITE/READ access by the memory transfer function The maximum operating frequency of SDRAM clock is 81MHz.
Others
High flexibility CPU I/F with 16bit CPU bus width and endian control are adopted. Built-in register is directly mapped to the 256 Bytes of CPU memory space. 176 pin plastic LQFP Pin lead coating is Pb free. (YGV628B-VZ) Operating temperature: -40 degree to +85 degree. CMOS, 3.3V unity voltage(5V tolerant)
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YGV628B
Block Diagram
Video Input I/F DRI[5:0] DGI[5:0] DBI[5:0] HSIN_N VSIN_N GCK1IN GCK2IN
To Clock Gen. To CRTC
Video Input Interface
Monitor I/F R, G, B DRO5-0 DGO5-0 DBO5-0 DBO5
Video Capture Controller
Data FORMAT CONV.
PRIORITY ENC.
Alpha Blending
Video Memory I/F SDQ[15:0] SA[13:0] SCS_N RAS_N CAS_N WE_N UDQM LDQM SDCKOUT
Data FORMAT CONV.
DAC
IREF CSYNC_N VSYNC VSYNC_N _N BLANK_N GCK1OUT GCK2OUT
DAC
Bitmap FIFO
Data FORMAT CONV.
FILTER
DAC
Video Memory Interface
CPU I/F D[15:0] A[23:1] CS_N WRH_N WRL_N RD_N WAIT_N READY_N INT_N DREQ_N RESET_N
DMA Control
Registers Registers
Clock
CRTC Clock Gen.
Color Palette
To blocks To all blocks
SYCKIN
CPU Interface
Examples of System Composition
Independent (self-propelled) system
RAM CPU Dot clock ROM AVDP7 SDRAM Analog RGB Digital RGB CRT LCD Encoder
Example of OSD to Digital Image (CPU, SDRAM, etc. are omitted)
Composite
External Image [16bitYCrCb] [ITU656]
AVDP7
Image + OSD
[16bitYCrCb] [ITU656]
DAC NTSC Encoder
Separate Component
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YGV628B
Example of OSD to Analog Image (CPU, SDRAM, etc. are omitted)
13.5MHz
AVDP7
YS_N
HSYNC,VSYNC Analog Image
[Analog RGB] Analog Switch Analog Image
Example of application to liquid crystal television (CPU, SDRAM, etc. are omitted)
External Image [NTSC]
NTSC Decoder
External Image [16bitYCrCb]
AVDP7
Image + OSD [18bitRGB]
LCD e.g.) 640x480
Capture + Interlace Progressive Conversion
Example of application to on-board multi-vision (CPU, SDRAM, etc. are omitted)
TV External Image [18bitRGB] [16bitYcrCb] [ITU656]
AVDP7
Image + OSD [18bitRGB]
LCD e.g.) 800x480
Capture + Resolution Conversion e.g.) 720x480/2 [4:3] 720x360/2 [16:9] 720x346/2 [1.85:1] 720x270/2 [2.35:1] [ ]= aspect ratio
800x480
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YGV628B
Example of application to digital image equipment (CPU, SDRAM, etc. are omitted)
AVDP7 [ITU656]
Analog Image
NTSC Decoder
Image+OSD [ITU656]
CRT / LCD
Digital Image
MPEG Decoder
Image through [ITU656] [ITU656]
Aux. Video
Example of application to digital recording equipment (CPU, SDRAM, etc. are omitted) Broadcasting Image [ITU656] AVDP7 Image + OSD [ITU656]
CRT / LCD
Recorded Image [ITU656] Recording System
Image through [ITU656]
MPEG Decoder
MPEG Encoder
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YGV628B
Pin Table
Pins Name Numbers I/O Functions Level 5Tr Drive
CUP Interface D15-0 A23-1 CS_N RD_N WRH_N WRL_N WAIT_N READY_N INT_N DREQ_N RESET_N SDQ15-0 SA13-0 SCS_N RAS_N CAS_N WE_N UDQM LDQM SDCKOUT Monitor Interface R,G,B IREF DRI5-0 DGI5-0 DBI5-0 HSIN_N VSIN_N YS_N DRO5-0 DGO5-0 DBO5-0 VSYNC_N CSYNC_N BLANK_N GCK1OUT GCK2OUT 3 1 6 6 6 1 1 1 6 6 6 1 1 1 1 1 O I I I I I O O O O O O O O O / No Analog R, G, B, Signals Output DAC Reference Electric-current Input Digital R Signal Input Digital G Signal Input Digital B Signal Input Horizontal Synchronized Signal Input Vertical Synchronized Signal Input YS Signal Output Digital R Signal Output Digital G Signal Output Digital B Signal Output Vertical Synchronized Signal Output Horizontal Synchronized Signal / Compound Synchronized Signal Output Non-display Interval Output Dot Clock Output 1 Dot Clock Output 2 x Drive Driving Capability Analog Analog LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL x x x x x x x x x x x 16 23 1 1 1 1 1 1 1 1 1 16 14 1 1 1 1 1 1 1 I/O I I I I I O O O O I I/O O O O O O O O O CPU Data Bus CPU Address Bus Chip Select READ Pulse Input WRITE Strobe Input/D15-8 WRITE Strobe Input/D7-0 CPU Bus WAIT (3-State Output) CPU Bus Ready (3-State Output) Interrupt Direct Memory Access Reset Input Video Memory Data Bus Video Memory Address Bus Video Memory Chip Enable Video Memory Low Address Strobe Output Video Memory Column Address Strobe Output Video Memory WRITE Enable Video Memory Data Mask Output/ SDQ15-8 Video Memory Data Mask Output/ SDQ7-0 Video Memory Clock Output LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVCMOS LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL LVTTL x x x x x x x x x x 4mA
4mA 4mA 4mA 4mA
Video Memory Interface 4mA 4mA 4mA 4mA 4mA 4mA 4mA 4mA 8mA
4mA 4mA 4mA 4mA 4mA 4mA 4mA 4mA 4mA
5Tr : 5V supply Yes/No Yes
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YGV628B
Pins Name Numbers I/O Functions Level 5Tr Drive
Clock GCK1IN GCK2IN SYNCKIN FILTER Power Supply VDD VSS PLLVDD PLLVSS DACVDD DACVSS TEST Pin TEST2-0_N 3 I / No Test Pin: Input H Level x Drive Driving Capability LVTTL 5Tr : 5V supply Yes/No Yes 15 17 1 1 1 1 Power Supply for Digital Circuit Part Ground for Digital Circuit Part Analog Power Supply for built-in PLL Ground for built-in PLL Analog Power Supply for built-in DAC Analog Ground for built-in DAC x x x x x x 1 1 1 1 I I I Dot Clock Input1 Dot Clock Input 2 System Clock Input Filter Connect Pin for PLL LVTTL LVTTL LVTTL Analog x
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YGV628B
Pin Assignment
VDD BLANK_N YS_N DBO5 DBO4 VSS
GCK2OUT VSS
VDD DGO3 DGO2
VSS DGO1
DGO0 DRO5 DRO4
DBO3
DBO2 DBO1 DBO0
DBO5 DBO4
DRO3 DRO2 DRO1 DRO0 VDD
SA0 SA8 SA10 SA9
SA12 SA11
132 131
130 129 128 127
126
125 124 123
122 121 120
119 118
117
116 115
114 113 112
111
110 109 108 109
106 105 104 103 102 101
100 99
98 97
96
95 94
93 92
91 90
89 82 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
VDD SA13
SA2 VDD SA7
SA6 SA1 VSS
SA4 SA3
SA5
DACVSS R G B IREF DACVDD TEST2_N TEST1_N TEST0_N CSYNC_N VSYNC_N GCK1OUT VDD GCK2IN DRI0 VSS DRI1 DRI2 DRI3 DRI4 DRI5 DGI0 DGI1 DGI2 DGI3 VDD DGI4 VSS DGI5 DBI0 DBI1 DBI2 DBI3 DBI4 DBI5 HSIN_N VSIN_N VDD VSS GCK1IN SYCKIN PLLVDD PLLVSS FILTER
133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 1 2 3 4 5 6 7 8 9
SCS_N VSS RAS_N SDCKOUT CAS_N UDQM WE_N VSS LDQM VDD SDQ8 SDQ7 SDQ9 SDQ6 VSS SDQ10 SDQ5 SDQ11 SDQ4 VDD SDQ12 VSS SDQ3 SDQ13 SDQ2 SDQ14 SDQ1 VSS SDQ15 SDQ0 VDD D0 D1 D2 D3 VSS D4 D5 D6 D7 D8 D9 VDD D10
WRH_N WRL_N
VSS A7 A6
RD_N RESET_N
DREQ_N INT_N
A10 A9 A8
A5
A4 A3
A2
A1
VSS CS_N VDD
D15 D14
D13
D12 VSS
A23
A22 A21 A20
A19 VSS A18
A17
A16 A15 A14 A13
VDD
A12 A11
VDD

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READY_N WAIT_N
D11
YGV628B
Pin Assignment Table
No. Terminal name I/O No. Terminal name I/O No. Terminal name I/O No. Terminal name I/O
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
A23 A22 A21 A20 VDD A19 VSS A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 VDD VSS A7 A6 A5 A4 A3 A2 A1 WRH_N WRL_N RD_N RESET_N VSS CS_N VDD DREQ_N INT_N READY_N WAIT_N D15 D14 D13 D12 VSS D11
I I I I I I I I I I I I I I I I
I I I I I I I I I I Ist I O O OT OT I/O I/O I/O I/O I/O
45 D10 46 VDD 47 D9 48 D8 49 D7 50 D6 51 D5 52 D4 53 VSS 54 D3 55 D2 56 D1 57 D0 58 VDD 59 SDQ0 60 SDQ15 61 VSS 62 SDQ1 63 SDQ14 64 SDQ2 65 SDQ13 66 SDQ3 67 VSS 68 SDQ12 69 VDD 70 SDQ4 71 SDQ11 72 SDQ5 73 SDQ10 74 VSS 75 SDQ6 76 SDQ9 77 SDQ7 78 SDQ8 79 VDD 80 LDQM 81 VSS 82 WE_N 83 UDQM 84 CAS_N 85 SDCKOUT 86 RAS_N 87 VSS 88 SCS_N
O : Output,
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O
89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
SA13 VDD SA11 SA12 SA9 SA10 SA8 SA0 VSS SA1 SA6 SA7 VDD SA2 SA5 SA3 SA4 VSS GCK2OUT VDD DRO0 DRO1 DRO2 DRO3 DRO4 DRO5 DGO0 DGO1 VSS DGO2 DGO3 VDD DGO4 DGO5 DBO0 DBO1 DBO2 DBO3 VSS DBO4 DBO5 YS_N BLANK_N VDD
O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O
133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176
DACVSS R G B IREF DACVDD TEST2_N TEST1_N TEST0_N CSYNC_N VSYNC_N GCK1OUT VDD GCK2IN DRI0 VSS DRI1 DRI2 DRI3 DRI4 DRI5 DGI0 DGI1 DGI2 DGI3 VDD DGI4 VSS DGI5 DBI0 DBI1 DBI2 DBI3 DBI4 DBI5 HSIN_N VSIN_N VDD VSS GCK1IN SYCKIN PLLVDD PLLVSS FILTER
O O O
I I I O O O I I I I I I I I I I I I I I I I I I I I I
I I
I : Input, 1st : schmitt trigger input, I/O : Input/Output
Od : Open drain output,
OT : 3-state output,
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YGV628B
Pins Functions
AVDP7 operates with a 3.3V power supply. Therefore, input and output of the interface to the peripheral circuits operates at LVTTL (3.3v)except RESET_N pin. However, the tolerant voltage to Input/Output signals are guaranteed up to 5V, therefore, connection to a 5V TLL level compatible device is also possible. Please use a register separately for each pin when making pull-up or pull-down of I/O pins outside of the device. However, when an input signal is fixed by pull-up or pull-down resistor, a common resistor can be used for these input pins.
1) Power Supply
AVDP7 is the 3.3V single power supply specification. In addition, exclusive analog power supply pins are prepared for the built-in PLL and the built-in DAC respectively. Be sure to observe the following instructions when performing power-on and power-off. Simultaneous power-on and power-off is the rule. When a time difference occurs due to the design, please follow the following order of power-on and power-off. Please perform power-on and power-off so that PLLVDD does not become higher than VDD. The order of power-on and power-off. At the time of power-on. VDD(Digital power supply) PLLVDD(Analog power supply for PLL) DACVDD(Analog power supply for DAC)
Signals.
At the time of power-off Signals DACVDD(Analog power supply for DAC) PLLVDD(Analog power supply for PLL) VDD(Digital power supply). When power-on and power-off are performed in reverse order against a recommended procedure in two kinds of power supplies in any of the power supplies mentioned above, a problem might be occurred to have an influence on the reliability of LSI. For the reason, please avoid such operations. VDD (Power Supply Pin No.5, 19, 34,46, 58, 69, 79, 90, 101, 108, 120, 132, 145, 158, 170) VSS (Power Supply Pin No.7, 20, 32, 43, 53, 61, 67, 74, 81, 87, 97, 106, 117, 127, 148, 160, 171) Power Supply Pin for Internal Digital Circuit. Please supply 3.3V to VDD pins, and supply a ground level to VSS pin. PLLVDD (Power Supply Pin No.174) PLLVSS (Power Supply Pin No.175) It is an analog power supply pin for built-in PLL. Please supply a ground level to PLLVSS pins, and supply 3.3V to PLLVDD. Be sure to perform power supply power-on and power-off, so that PLLVDD may not become higher than VDD.
DACVDD (Power Supply Pin No.138) DACVSS (Power Supply Pin No.133) It is an analog power supply pin for built-in DAC. Please supply 3.3V to DACVDD pin, and supply a ground level to DACVSS pin. Be sure to supply separately to other power supplies.
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YGV628B
2) Clock
To AVDP7, a clock (dot clock) for a scan timing of monitor display, and for passing a display data, a clock (capture clock) for capturing a digital image input, and a clock (system clock) which is used for other process are supplied separately. Please input a dot clock and a capture clock into GCK1IN pin and GCK2IN pin, and input a system clock into SYCKIN pin. Since there is no function of XTAL oscillation, be sure to input the clock which carried out the external oscillation.
GCK1IN (Input Pin No.172) GCK2IN (Input Pin No.146) These are input pins of a dot clock and a capture clock. Be sure to input the 5MHz to 40MHz clock oscillated externally into these pins. SYCKIN (Input Pin No. 173) It is a system clock input pin. The reference clock for the built-in PLL is input. Be sure to input the 5MHz to 40MHz clock into SYCKIN. FILTER (Analog Pin No.176) It is the filter connection pin for built-in PLL used for a system clock oscillation. Please connect a resistor and a capacitor externally between PLLVSS pin and FILTER pin.
3) CPU Interface
D15-0 (Input/Output Pin No. 39-42, 44, 45, 47-52, 54-57) It is a CPU data bus pin. It connects with an external data bus of CPU. Since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device. A23-1(Input Pin No. 1-4, 6, 8-18, 21-27) It is a CPU address bus pin. It connects with an external address bus of CPU. Since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device if necessary. CS_N (Input Pin No.33) It is a chip select input pin. The chip select signals from CPU to register space or video memory space are input. Since this pin does not internally have a pull-up resistor, please make the pull-up outside of the device if necessary. This signal is low active. RD_N (Input Pin No.30) It is a READ pulse input pin. The strobe signal for data read-out from CPU is input. Since this pin does not internally have a pull-up resistor, please make the pull-up outside of the device if necessary. This signal is low active. WRH_N (Input Pin No.28) WRL_N (Input Pin No. 29) It is a WRITE pulse input pin. The strobe signal for data writing from CPU is input. Since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device if necessary.

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YGV628B
These signals are low active.
WAIT_N (3-state Output Pin No.38) It is a CPU bus WAIT pin. The bus WAIT demand signal to CPU is output. Since this pin does not internally have a pull-up resistor, please make the pull-up outside of the device. This signal is low active. READY_N (3-state Output Pin No.37) It is a CPU bus READY pin. The bus READY signal to CPU is output. Since this pin does not internally have a pull-up resistor, please make the pull-up outside of the device. This signal is low active. INT_N (Output Pin No.36) It is an interrupt signal output pin. The interrupt request signal to CPU is output. This signal is low active. DREQ_N (Output Pin No.35) It is a DMA request signal output pin. The DMA request signal to CPU is output. This signal is low active.
4) Video Memory Interface
SDQ15-0 (Input/Output Pin No. 59, 60, 62-66, 68, 70-73, 75-78) It is a data input/output bus pin for video memories. It connects with the data bus of a video memory. Since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device. SA13-0 (Output Pin No. 89, 91-96, 98-100, 102-105) It is an address bus output pin for video memories. It connects with the address bus of a video memory. The signal attribute output from SA13-0 pin differs according to the kind of external SDRAM. SCS_N (Output Pin No.88) It is a tip select output pin for video memories. The tip select signal to a video memory is output. This signal is low active. RAS_N (Output Pin No.86) It is a low address strobe output pin for video memories. The low address strobe signal to a video memory is output. This signal is low active. CAS_N (Output Pin No.84) It is a column address strobe output pin for video memories. The column address strobe signal to a video memory is output. This signal is low active. WE_N (Output Pin No.82) It is a WRITE strobe output pin for video memories. The WRITE strobe signal to a video memory is output. This signal is low active.

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YGV628B

UDQM (Output Pin No.83) LDQM (Output Pin No.80) It is a data mask signal output pin for video memories. The data mask signal to a video memory is output. UDQM pin is a data mask signal SDQ15-8 pin, and LDQM pin is a data make signal to SDQ7-0. These signals are high active. SDCKOUT (Output Pin No.85) It is a clock output pin for video memories. The clock to a video memory is output. The clock frequency output from this pin is 75MHz to 81MHz.
5) Monitor Interface

R (Analog Output Pin No.134) G (Analog Output Pin No.135) B (Analog Output Pin No.136) It is an analog RGB output pin. Linear R, G, and B signal are output. When the analog RGB output is not used, please connect nothing. IREF (Analog Pin No.137) It is a standard current input pin for RGB DAC. When an analog RGB output is not used, please connect nothing. DRO5-0 (Output Pin No.109-114) DGO5-0 (Output Pin No.115, 116, 118, 119, 121, 122) DBO5-0 (Output Pin No.123-126, 128, 129) It is a digital RGB output pin. When a digital RGB output is not used, please connect nothing. DRI5-0 (Input Pin No.147, 149-153) DGI5-0 (Input Pin No.154-157, 159, 161) DBI5-0 (Input Pin No.162-167) It is a digital RGB input pin. Since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device if necessary. VSYNC_N (Output Pin No.143) It is a vertical synchronized signal output pin. Vertical synchronized signal is output. This signal is low active. CSYNC_N (Output Pin No.142) It is a horizontal / composite synchronized signal output pin. Horizontal synchronized signal or Composite synchronized signal are output. This signal is low active. HSIN_N (Input Pin No.168) It is a horizontal synchronized signal input pin. The external horizontal synchronized signal for resetting an internal horizontal counter is input. When not used, please make the pull-up outside of the device if necessary because this pin does not internally have a pull-up resistor.

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YGV628B
This signal is low active.
VSIN_N (Input Pin No.169) It is a vertical synchronized signal input pin. The external vertical synchronized signal for resetting an internal vertical counter is input. When not used, please make the pull-up outside of the device if necessary because this pin does not internally have a pull-up resistor. This signal is low active. BLANK_N (Output Pin No.131) It is a display timing output pin. The signal which shows a no-display period is output. This signal is low active. YS_N (Output Pin No.130) It is YS signal output pin. YS signal at the time of superimpose is output. This signal is low active. GCK1OUT (Output Pin No.144) GCK2OUT (Output Pin No.107) It is a dot clock output pin. A dot clock is output.

6) System Reset
RESET_N (Schmitt trigger type input Pin No.31) It is a reset pin. Please input a power-on reset signal. The reset signal input having predetermined period is surely required at the power-on. Since this pin does not internally have a pull-up resistor, please make the pull-up outside of the device if necessary. This signal is low active. This pin uses the schmitt trigger type buffer.
7) LSI Test
TEST2-0_N (Input Pin No. 139, 140, 141) It is a test mode setting pin for a device test. Since these pins do not internally have a pull-up resistor, please make the pull-up outside of the device.
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YGV628B
Electrical Characteristics
Absolute Maximum Ratings
Items Power Supply Voltage (VDD Pin) DAC Power Supply Voltage (DACVDD pin) PLL Power Supply Voltage(PLLVDD pin) Input Pin Voltage Output Pin Voltage (5V tolerant Pin) Output Pin Voltage (Other than Above) Output Pin Electric Current Storage Temperature Symbol VDD VDAC VPLL VI VO VO IO Tstg Rating -0.5 to +4.6 -0.5 to +4.6 -0.5 to +4.6 -0.5 to +5.5 -0.5 to +5.5 -0.5 to VDD+0.5 -20 to +20 -50 to +125 Unit V V V V V V mA C Note 1 1 1 1 1 1
Note 1) Value based on Vss(GND) =0V
Recommended Operating Condition
Items Power Supply Voltage DAC Power Supply Voltage (DACVDD pin) PLL Power Supply Voltage (PLLVDD pin) Ambient Operation Temperature Symbol VDD VDAC VPLL TOP Min 3.0 3.0 3.0 -40 Typ 3.3 3.3 3.3 Max 3.6 3.6 3.6 +85 Unit V V V C Note 1 1 1 2
Note 1) Value based on Vss(GND) =0V Note 2) The board wiring density is estimated to be 260% or over.
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YGV628B
DC Characteristics
Items Low Level Input Voltage (RESET_N pin, TEST2-0_N pin) Low Level Input Voltage (except RESET_N pin, TEST2-0_N pin) High Level Input Voltage (RESET_N pin, TEST2-0_N Pin) High Level Input Voltage (except RESET_N pin, TEST2-0_N pin) Built-in DAC Recommended Operation Condition Reference Current (IREF Pin) Output Load (R,G,B) Symbol VIL VIL VIH VIH Min -0.3 -0.3 VDDx0.8 2.0 Typ Max VDDx0.2 0.8 5.5 5.5 Unit V V V V Note 1 1 1 1
-9.38 37.5
mA
Note 1) Value based on Vss(GND) =0V
Items Low Level Output Voltage High Level Output Voltage Input Leakage Current Output Leakage Current Total Power Consumption Consumption Current Items VDD DACVDD PLLVDD
Condition IOL=100A IOH= -100A
CL=20pF CL=20pF When 0V output When 81MHz
Symbol VOL VOH ILI ILO PD IVDD IDAC IPLL
Min 0 2.4 -10 -25
Typ
Max 0.4 VDD +10 +25 1.2 230 80 2.5
Unit V V A A W mA mA mA
Note
2 3 3 3 3
Note 2) Be sure to use the resistance less than 7kwhen connecting an external pull-up resistance. The minimum and the maximum of input leak current are a value when having not connected external resistance. Note 3) VIL = GND, VIH = VDD for consumption current and power consumption value.
Items Input Pin Capacitance Output Pin Capacitance Input/Output Pin Capacitance
Symbol CI CO CIO
Min
Typ
Max 10 10 10
Unit pF pF pF
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YGV628B
AC Characteristics NOTE : A timing measurement level is 1.4V and input signal transient time is 1ns. Clock Input
No. 1 2 3 4 Item SYCKIN Input Clock Frequency SYCKIN Clock Cycle Time SYCKIN Clock High Level Pulse Width SYCKIN Clock Low Level Pulse Width MCLK(PLL Out) Clock Frequency MCLK(PLL Out) Clock Cycle Time Symbol fSYCK tcSYCK twhSYCK twlSYCK fMCLK tcMCLK Min 5 25 7.5 7.5 75 13.3 Typ Max 40 200 Unit MHz ns ns ns MHz ns
81 12.3
1 2 3
1.4V
Reset Input and Power Supply
No. Item Symbol Min Typ Max Unit
1 2 3 4 5 6
RESET_N Pin Input Time (respect to SYCKIN) RESET_N Pin Input Time (respect to VDD) VDD-RESET_N Pin Setup Time PLL Lock up Time Time Difference in Power-on Time Difference in Power-off
twRES1 twRES2 tsRES twPLU tVSKWR tVSKWF
1 1 0 10 1 1
s s s ms s s
Power supply rose up first Power supply rose up last SYCKIN RESET_N 3 R_SR1
50% of the recommended operating voltage (TYP)
5
Min. of the recommended operating voltage 50% of the recommended operating voltage (TYP)
VIL
2
1
VIH VIL
4
PLL playback clock
Power supply fell down first Power supply fell down last
50% of the recommended operating voltage (TYP)
6
50% of the recommended operating voltage (TYP)
-17-
YGV628B
CPU Interface (Measurement Condition : CL=20pF)
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Item A23-1 : setup time A23-1 : hold time CS_N: setup time CS_N: hold time D15-0 : output data turn on time D15-0 : output data turn off time D15-0 : output data valid delay time D15-0 : output data hold time WAIT_N, READY_N: turn on time WAIT_N, READY_N: valid delay time WAIT_N,READY_N: turn off time D15-0 : input data setup time D15-0 : input data hold time WRx_N: hold time READY_N: hold time from WRx_N, RD_N inactive Symbol tsA thA tsCS thCS tonD toffD tdD thD tonWAIT tdWAIT toffWAIT tsD thD thWR thREADY Min 1 0 1 0 0 Typ Max Unit Note 1 1 2 2
10 0 0 0 15 15 tcMCLK+10 0 0 0 12 3 3 ns
Note 1) This is a regulation for WRH_N, WRL_N, and RD_N signals. However, in case of CS_N control, it is a rule for CS_N. Note 2) They are the conditions of being WRH_N, WRL_N, and RD_N control. It becomes CS_N control when not filling this regulation. Note 3) D15-8 is the regulation to WRH_N. D7-0 is the regulation to WRL_N. CPU READ Cycle
A23-1
1 2
CS _N
3 4
RD_N
8 5
6
D15-0 WAIT _N
Hi gh-z 10 9 Hi gh-z 7 11
High-z
High-z
7
15
11 High-z
READY_N
9 Hi gh-z
-18-
YGV628B
CPU WRITE Cycle
A23-1
1 2
CS_N
3 4
WRx_N
12 13
D15-0
10 9 14 11 High-z
WAIT_N
High-z
10
15
11 High-z
READY_N
9 Hi gh-z
-19-
YGV628B
SDRAM Interface (Measurement Condition: CL=15pF)
No. 1 2 3 4 5 6 7 8 Item SDCKOUT: jitter SDCKOUT: frequency SDCKOUT: cycle time SDCKOUT: clock high level width SDCKOUT: clock low level width SDQ15-0 : input data setup time SDQ15-0 : input data hold time SCS_N, RAS_N, CAS_N, WE_N, SA13-0, SDQ15-0, UDQM, LDQM : output delay time SCS_N, RAS_N, CAS_N, WE_N, SA13-0, SDQ15-0, UDQM, LDQM : output hold time Symbol
tjSDCK fSDCK tcSDCK twhSDCK twlSDCK tsSDQ thSDQ tdSDO thSDO
Min -1 75 12.35 3.5 3.5 4 1
Typ
Max 1 81 13.33
Unit ns MHz
Note
1 1,2 1,3 1 1 1 1 1 1
ns 9
1.5
Contents of Mode Register Read/Write Mode CAS Latency Wrap Type Burst Length Command Interval Clock Cycle Time (CL=2) Ref/Active - Ref/Active Command Interval Pre-charge - Active Command Interval WRITE Recovery Time Data in - Command Interval Active - Pre-charge Command Interval Active - Read / Write Command Delay Time Mode Register Set Cycle Time Note 1) Note 2) Note 3) Note 4) Note 5)
Burst Read and Burst Write 2 Sequential 2 4 tCK2 tRC tRP tWR tDAL tRAS tRCD tRSC Less than 10 ns Six or less cycle (in case of SDCKOUT frequency 81 MHz, less than 74ns) Two or less cycle (in case of SDCKOUT frequency 81 MHz, less than 24ns) Two or less cycle (in case of SDCKOUT frequency 81 MHz, less than 24ns) Four or less cycle (in case of SDCKOUT frequency 81 MHz, less than 49ns) Five or less cycle (in case of SDCKOUT frequency 81 MHz, less than 61ns) Two or less cycle (in case of SDCKOUT frequency 81 MHz, less than 24ns) Four or less cycle (in case of SDCKOUT frequency 81 MHz, less than 49ns) 5
PLL must be in stable state. Fulfill a condition fSDCK fGCK1O x 2 Fulfill a condition tcSDCK x 2 tcGCK1O Conditions of SDRAM to be chosen. Although some SDRAM makers may have divided and specified the interval from the auto-refresh to the following command (tRRC), it is necessary to be lower than tRC.
-20-
YGV628B
1 1
SDCKOUT
3 2 4
5
6
SDQ[15:0] (input)
7 8
Outputs
Outputs SCS_N, RAS_N, CAS_N, WE_N, SA13-0, SDQ15-0(output), UDQM, LDQM
-21-
YGV628B
Display Timing Signals (Measurement Condition : CL=20pF)
No. 1 2 3 4 5 6 Item GCK1IN, GCK2IN : frequency GCK1IN, GCK2IN : cycle time GCK1IN, GCK2IN : clock high level width GCK1IN, GCK2IN : clock low level width HSIN_N, VSIN_N, DRI5-0, DGI5-0, DBI5-0: input data setup time HSIN_N,VSIN_N,DRI5-0, DGI5-0, DBI5-0: input data hold time GCK1OUT: delay time GCK2OUT: delay time GCK1OUT : frequency GCK1OUT : cycle time GCK2OUT : frequency GCK2OUT : cycle time GCK1OUT, GCK2OUT : clock duty YS_N, CSYNC_N, VSYNC_N, BLANK_N, DRO5-0, DGO5-0, DBO5-0: output delay time YS_N, CSYNC_N, VSYNC_N, BLANK_N, DRO5-0, DGO5-0,DBO5-0: output hold time Symbol fGCKI tcGCKI twhGCKI twlGCKI tsDI thDI tdGCK1O tdGCK2O fGCK1O tcGCK1O fGCK2O tcGCK2O tduGCKO tdDISP1 thDISP1 0 Min 5 25 8 8 3 1 0 0 5 25 5 25 45 20 20 40 200 40 200 55 9 Typ Max 40 200 Unit MHz ns ns ns ns ns ns ns MHz ns MHz ns % ns ns Note 1 2
7 8 9 10
3
Note 1) Note 2) Note 3)
Fulfill a condition fSDCK fGCK1Ox2 Fulfill a condition tcSDCKx2 tcGCK1O In the cases of other than Analog synchronization
GCK1IN OR GCK2IN
2 1 3
4
5
Inputs
6 6 6
GCK1OUT OR GCK2OUT
8 7 9 10 8
Outputs
Inputs HSIN_N, VSIN_N, DRI5-0, DGI5-0, DBI5-0 Outputs YS_N, CSYNC_N, VSYNC_N, BLANK_N, DRO5-0, DGO5-0, DBO5-0
-22-
YGV628B
Analog Characteristics In AVDP7, R, G, and B pin is an output pin for an Analog signal. RGB Pin Output Characteristics Item Resolution Settling Time Output Propagation Delay Time Output Voltage Amplitude (Vp-p) Max Output Voltage (VWHITE) Min Output Voltage (VBLACK) Vp-p Deviation of R, G, B Condition RL = 37.5 CL = 30 pF IREF = -9.38mA Additional capacity of GCK1OUT = 20pF
Min Type Max
8 20 -5 0.7 0.7 0 3 3
Unit bit ns ns V V V %
Settling time is defined as the interval between the point at which DAC output level comes up to 50% and the point at which the output level reaches and stays within 1 LSB centered on the resulting output level. Output Propagation Delay Time is defined as the interval between the rising edge of GCK1OUT and the point at which DAC output level comes up to 50%.
GCK1OUT
1 LSB R G B 1 LSB Output propagation delay time Settling Time
50 %
Measurement Circuit R,G,B RL CL
-23-
YGV628B
Package Outline Drawing
-24-
YGV628B
-25-
YGV628B

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